1. Field of the Invention
This invention relates to integrated circuits and specifically to integrated memories which may be repaired by activating redundant elements to replace defective elements, and to a technique of identifying repaired elements.
2. Description of the Prior Art
Electronic memories are accessed by applying to their address terminals binary signals representing the address of the desired memory element. Decoder circuits in the memory use the bit values of the address to operate switches, typically transistors, in lines between each of the memory elements and the data input/output (I/O) terminals. The logic of the decoder circuits produces a complete set of enabling signals to close the set of switches between the addressed memory location and the I/O terminals, and an incomplete set for the switches between all other memory locations and the I/O terminals. The desired memory location may then be read from or written to.
A relatively recent development in the manufacture of integrated circuits (ICs) is the provision of on-chip redundant circuit elements to improve IC manufacturing yields and economy. Defective memory cells are repaired through operations on fuses to substitute the use of extra rows and/or columns of memory cells and associated extra decoder circuits. When testing reveals a defective cell in the memory, a spare decoder circuit is customized to respond to the addresses of the defective row (or column) such that a spare row (or column) is accessed in place of the defective row (or column). According to one repair technique, the defective row (or column) is disconnected permanently from its associated decoder by laser pulse vaporization of fuses. This technique is discussed by R. P. Cenker, et al. in "A Fault-tolerant 64K Dynamic RAM," published in the Digest of Technical Papers, pages 150, 151 and 290, from the IEEE International Solid State Circuit Conference, February 1979. According to another repair technique, the defective row (or column) is disabled through on-chip logic whenever the customized spare decoder is selected. This technique is discussed by K. Kokkonen, et al. in "Redundancy Techniques for Fast Static RAMs," published in the Digest of Technical Papers, pages 80 and 81, from the IEEE International Solid State Circuit Conference, February 1981. A satisfactorily repaired IC is normally indistinguishable from an originally perfect IC.
Testing repaired memories is a problem because the data pattern has been physically altered. Even if defective memory cells have been disconnected and replaced by good cells and the memory can be tested and determined to be satisfactory, its reliability is questionable because certain kinds of defects may propagate during the operational life of the memory, and affect adjacent cells rendering the memory unusable sooner than an originally good memory. To isolate the failure rates of repaired memories from originally good memories, it is important to know whether subsequently failed cells are adjacent to repaired cells. Therefore, a need exists to identify repaired elements in packaged integrated circuits to determine the relative position of the subsequently failed elements with respect to the position of originally defective and repaired elements.